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DDR is Double Data Rate RAM, it is SDRAM however DDR RAM can be accessed on the ups and downs of a clock cycles (Like a rolla coaster) however with SDRAM only access on the downs.

CAS is refereced to as CAS Latency, this is the amount of cycles it takes between activating the CAS signal/address and the placing of the single bit/data onto the register in which can be then taken up the databus to the CPU to process.

Try to think like this: The lower the CAS the better

CL2.5 2 2 6

Is equal to:

Overal latency is 2.5
CAS Latency is 2
RAS-CAS Delay 2
RAS precharge 6

CAS Latency is the time delay between the inputting of the COLOMN address into address pins/activation of CAS signals and the reading of data from the pins. The higher the value the longer the wait to read the data, if CL3 then 3 cycles need to pass before you can read the data. This is where the cell is discharged (where the data is read) and then recharged to its original state.

RAS Precharge is used to charge the cells before the accessing (read/write) of the cell occurs; this is because when the memory is being accessed it cannot be charged simultaneously and the cell may lose its charge (due to leaking) so before the accessing takes place the memory is precharged.



RAS-CAS Delay is the amount of clock cycles, which take place between the activation of the row address using the RAS signal and the sending of the column address to the address pins. RAS-CAS Delay involves different tasks including CAS Precharge.